? semiconductor components industries, llc, 2006 october, 2006 ? rev. 0 1 publication order number: nlas7222a/d nlas7222a 3.3 v, wide bandwidth, 2? to ?1?port (dpdt) switch with enable on semiconductor?s nlas7222a series of analog switch circuits are produced using the company?s advanced sub?micron cmos technology, achieving industry?leading performance. the nlas7222a is a 2? to 1?port analog switch. its wide bandwidth and low bit?to?bit skew allow it to pass high?speed differential signals with good signal integrity. the switch is bidirectional and offers little or no attenuation of the high?speed signals at the outputs. industry?leading advantages include a propagation delay of less than 250 ps, resulting from its low channel resistance and low i/o capacitance. its high channel?to?channel crosstalk rejection results in minimal noise interference. its bandwidth is wide enough to pass high?speed usb 2.0 differential signals (480 mb/s). features ? r on is typically 6.5 at v cc = 3 v ? low bit?to?bit skew: t ypically 50 ps ? ovt on d+ and d? up to 3.6 v ? power off protection: when v cc = 0 v, d+ and d? can tolerate up to 3.6 v ? low crosstalk: ?45 db @ 250 mhz ? low current consumption: 1 a ? near?zero propagation delay: 250 ps ? channel on?capacitance: 6.5 pf (typical) ? v cc operating range: +3.0 v to +3.6 v ? > 720 mhz bandwidth (or data frequency) ? this is a pb?free device typical applications ? differential signal data routing ? usb 2.0 signal routing important information ? continuous current rating through each switch 50 ma http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information http://onsemi.com marking diagram xx m xx = specific device code m = date code = pb?free device wqfn?10 case 488aq 1
nlas7222a http://onsemi.com 2 figure 1. pin connections and logic diagram (top view) 8 9 10 12 76 5 4 3 hsd1+ hsd2+ hsd1? hsd2? d? gnd d+ oe v cc s control table 1. pin description pin function s select input oe output enable hsd1+, hsd1?, hsd2+, hsd2?, d+, d? data ports table 2. truth table oe s hsd1+, hsd1? hsd2+, hsd2? 1 0 0 x 0 1 off on off off off on maximum ratings symbol parameter value unit v cc positive dc supply voltage ?0.5 to +4.6 v v is analog switch input voltage hsd1+, hsd1?, hsd2+, hsd2? d+, d? ?0.5 to v cc + 0.3 ?0.5 to +4.6 v v in digital select input voltage ?0.5 to +4.6 v i d continuous dc current (through analog switch) 50 ma p d power dissipation 0.5 w t s storage temperature ?65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. recommended operating conditions symbol parameter min max unit v cc positive dc supply voltage 3.0 3.6 v v is analog i/o voltage (hsd1+, hsd1?, hsd2+, hsd2?) gnd v cc v v os analog common output voltage (d+, d?) gnd 3.6 v v in digital select input voltage gnd v cc v t a operating temperature range ? 40 + 85 c t r , t f input rise or fall time v cc = 3.3 v 0.3 v 0 15 ns
nlas7222a http://onsemi.com 3 dc electrical characteristics for usb 2.0 switching over operational range symbol parameter test conditions v cc (v) ? 40 c to +85 c unit min typ (note 1) max v ih input high voltage (v in ) 3.0 to 3.6 1.3 ? ? v v il input low voltage (v in ) 3.0 to 3.6 ? ? 0.5 v v ik clamp diode voltage i is = ?18 ma 3.0 ? ? ?1.2 v i cc quiescent supply current v is = v cc or gnd; i d = 0 a 3.6 ? ? 1.0 a i cct increase in i cc per control voltage v in = 2.6 v 3.6 ? ? 10.0 a i i input leakage current 0 v is v cc 3.6 ? ? 1.0 a i oz off state leakage 0 v is; v os v cc 3.6 ? ? 1.0 a i off power off leakage current (d+, d?) 0 v is; v os v cc 0 ? ? 1.0 a r on switch on?resistance v is = 0 to 0.4 v; i d = 8 ma 3.0 ? 6.5 9.0 r flat(on) on?resistance flatness v is = 0 to 1.0 v; i d = 8 ma 3.0 ? 2.0 ? r on on?resistance match from center ports to any other ports v is = 0 to 0.4 v; i d = 8 ma 3.0 ? 0.35 ? 1. typical values are at v cc = 3.3 v and t a = +25 c ac electrical characteristics symbol parameter test conditions v cc (v) ?40 c to +85 c unit min typ (note 2) max t on turn?on time v is = 0.8 v 3.0 to 3.6 ? 13.0 30.0 ns t off turn?off time v is = 0.8 v 3.0 to 3.6 ? 12.0 25.0 ns t bbm break?before?make delay v is = 0.8 v 3.0 to 3.6 2.0 4.7 6.5 ns t pd propagation delay c l = 10 pf 3.0 to 3.6 ? 0.25 ? ns o irr off?isolation f = 250 mhz; r l = 50 3.0 to 3.6 ? ?28 ? db x talk non?adjacent channel crosstalk f = 250 mhz; r l = 50 3.0 to 3.6 ? ?45 ? db bw ?3 db bandwidth r l = 50 ; c l = 0 pf 3.0 to 3.6 ? 720 ? mhz r l = 50 ; c l = 5 pf ? 500 ? ac electrical characteristics for usb 2.0 switching over operational range t sk(o) channel?to?channel skew c l = 10 pf 3.0 to 3.6 ? 0.05 ? ns t jitter total jitter r l = 50 ; c l = 10 pf t r = t f = 500 ps at 480 mbps 3.0 to 3.6 ? 0.2 ? ns 2. typical values are at v cc = 3.3 v and t a = +25 c capacitance symbol parameter test conditions ?40 c to +85 c unit min typ (note 3) max c in control pin input capacitance v cc = 0 v ? 4.5 ? pf c on hsd+, hsd? on capacitance v cc = 3.3 v; oe = 0 v ? 14 ? pf c off hsd+, hsd? off capacitance v cc = v is = 3.3 v; oe = 3.3 v ? 12 ? pf 3. typical values are at v cc = 3.3 v and t a = +25 c
nlas7222a http://onsemi.com 4 figure 2. t bbm (time break?before?make) output dut 50 35 pf v cc switch select pin output input v cc gnd figure 3. t on /t off 50% 50% 90% 90% t on t off v oh output input v cc 0 v figure 4. t on /t off dut open 35 pf v cc input 50% 50% 10% t on t off output input v cc 0 v 10% 50 0.1 f t bmm output v out v ol v out v oh v ol dut open v cc input output 50 35 pf v out 0.1 f 50 % of droop voltage droop
nlas7222a http://onsemi.com 5 channel switch control/s test socket is normalized. off isolation is measured across an off channel. on loss is the bandwidth of an on switch. v iso , bandwidth and v onl are independent of the input signal direction. v iso = off channel isolation = 20 log for v in at 100 khz v onl = on channel loss = 20 log for v in at 100 khz to 50 mhz bandwidth (bw) = the frequency 3 db below v onl v ct = use v iso setup and test to all other switch analog input/outputs terminated with 50 output dut input 50 50 generator reference transmitted figure 5. off channel isolation/on channel loss (bw)/crosstalk (on channel to off channel)/v onl 50 v out v in v out v in off on off v out v cc gnd output v in c l dut figure 6. charge injection: (q) v in open output
nlas7222a http://onsemi.com 6 applications information the low on resistance and capacitance of the nlas7222a provides for a high bandwidth analog switch suitable for applications such as usb data switching. results for the usb 2.0 signal quality tests will be shown in this section, along with a description of the evaluation test board. the data for the eye diagram signal quality and jitter tests verifies that the nlas7222a can be used as a data switch in low, full and high speed usb 2.0 systems. figures 7, 8 and 9 provide a description of the test evaluation board. the usb tests were conducted per the procedures provided by the usb implementers forum ( www.usb.org ), the industry group responsible for defining the usb certification requirements. the test patterns were generated by a pc and matlab software, and were inputted to the analog switch through usb connectors j1 (hsd1) or j2 (hsd2). a usb certified device was plugged into connector j4 to function as a data transceiver. the high speed and full speed tests used a flash memory device, while the low speed tests used a mouse. test connectors j3 and j5 provide a direct connection of the usb device and were used to verify that the analog switch does not distort the data signals. figure 7. schematic of the nlas7222a usb demo board
nlas7222a http://onsemi.com 7 figure 8. block diagram of the nlas7222a usb demo board figure 9. photograph of the nlas7222a usb demo board
nlas7222a http://onsemi.com 8 and8267/d ? nlas7222a usb 2.0 signal quality compliance tests figures 10, 11 and 12 show the test results for usb eye diagram tests. a summary of the usb tests is provided in table 3. the nlas7222a passes the low, full and high speed signal quality, eye diagram and jitter tests. application note and8267/d provides a detailed description of the usb 2.0 test results. figure 10. low speed signal quality eye diagram test (nlas7222a with v cc = 3.6 v) figure 11. full speed signal quality eye diagram test (nlas7222a with v cc = 3.6 v)
nlas7222a http://onsemi.com 9 figure 12. high speed signal quality eye diagram test (nlas7222a with v cc = 3.0 v) table 3. summary of the usb 2.0 signal quality tests results compliance test low speed full speed high speed signal quality test pass pass pass signal eye test pass pass pass eop width 1.29 ms 166.86 ns 7.98 bits measured signal rate 1.5140 mhz 12.0016 mhz 480.0685 mhz crossover voltage range 1.75 to 1.83 v, mean crossover = 1.78 v 1.70 to 1.73 v, mean crossover = 1.71 v n/a connective jitter range ?2.2 to 2.2 ns, rms jitter = 1.3 ns ?0.2 to 0.2 ns, rms jitter = 0.1 ns ?79.4 to 77.4 ps, rms jitter = 35.0 ps paired jk jitter range ?1.4 to 2.7 ns, rms jitter = 1.3 ns ?0.1 to 0.1 ns, rms jitter = 0.1 ns ?93.2 to 78.7 ps, rms jitter = 24.4 ps paired kj jitter range ?1.9 to 1.1 ns, rms jitter = 1.0 ns ?0.2 to 0.1 ns, rms jitter = 0.1 ns ?72.8 to 50.9 ps, rms jitter = 15.6 ps ordering information device order number device nomenclature package shipping ? circuit indicator technology device function tape & reel suffix NLAS7222AMTR2G nl as 7222 r2 wqfn?10 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nlas7222a http://onsemi.com 10 package dimensions wqfn10, 1.4x1.8x0.4p case 488aq?01 issue b a b a3 a1 0.08 c seating plane note 3 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. exposed pads connected to die flag. used as test contacts. dim min max millimeters a 1.40 bsc a1 0.40 bsc a3 0.70 0.80 b d 0.30 0.50 e e l l1 0.20 ref 0.00 0.050 pin 1 reference d a e b 0.15 c 2x 0.15 c 2x 0.10 c c l1 10 1 3 5 6 0.05 c 0.10 ca b 10 x e e/2 l 9 x 0.40 0.60 1.80 bsc 0.15 0.25 10 x pitch 1 9 x scale 20:1 0.663 0.0261 0.200 0.0079 0.400 0.0157 0.225 0.0089 2.100 0.0827 1.700 0.0669 0.563 0.0221 mm inches *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license un der its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in a ny manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 nlas7222a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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